Timing Verification in Corona Del Mar
Each project is different. Some projects have a fixed timing requirement passed down to the design and development team based on the client's requirements. Others are simply looking for the highest performance possible for a given implementation technology and yet others are looking for the lowest power solution. These last requirements are usually defined as finding the lowest EDP (energy delay product) which yields the optimal balance of power and performance.
The Role of a Timing Verification
In order to meet the performance goals of the project, timing is considered first in the architecture phase and then the RTL design & developments phase. These phases yield an objective detailed timing requirements for each module and the overall system. In order to meet these goals timing must be met in the synthesis and the physical place and route phases.
Our physical design team, in order to meet the timing goals, quickly close timing before and after place and route will develop a set scripts to control the EDA (Electronic Design Automation) tools that will be used to create the design through synthesis and a sub-set of that information, the timing constraints, are used to verify timing of the design both after synthesis and after place and route.
In reality, rarely do these scripts create a design that will pass timing on the first attempt. The timing results are fed back to the RTL design team to review. Revisions may then be made to the RTL and refinements to the scripts may also be made and the tools re-run. This iterative process is repeated until suitable results are obtained.