Simulation and Verification

As each RTL block of a design is completed by the designer it is simulated to verify its completeness and base functionality. It is then passed on to the verification team.

Simulators exercise a design by applying stimulus to the inputs, then pushing these signals through the design, modeling each logic step precisely to create outputs. These outputs are compared to the expected results to verify that the design is working as intended.

Advanced Architectures uses a number of different simulators. Some are small and efficient and designed to enable rapid development of the individual modules. Others are large fast engines that can crank millions of test through large complex designs to ensure the entire is functioning correctly.

We also us simulators to help design and verify small custom cells deep in the design. These custom cells are often the basis for the EDP (energy delay product) goals of the product.

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The Verification Plan

The Verification Plan is fundamental to the program and first pass silicon success. This effort will specifically require that all the technical team members provide an active contribution to this plan. The primary goal of this planning effort is to document the various operations and sub-operations that the ASIC or FPGA must be able to perform in order to meet system level functionality. The results of this Verification Plan effort will be an internal document that outlines a simulation plan in sufficient detail that engineers skilled in the art of digital design and verification can translate these requirements into specific simulation tests and environment to validate the design in a digital simulation tool.

This test plan may be validated through the use of code-coverage tools to explore to what degree the suite of tests (derived from the verification plan) have tested the logic implementation of the architecture.

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What Does Verification Involve?

This verification process represents the implementation of the above described verification plan. Advanced Architectures often propose that the client's technical team participate in the verification. One team checking the other generally leads to an optimal result. Status will be kept through a summary table of verification tests written and the status of failure or passing. All tests and the verification environment will be designed to incorporate self checking mechanisms and allow for variations and result arrival time due to changes in pipeline and detail design.

The verification environment may leverage Advanced Architecture’s verification environment that utilizes a behavioral RISC processor and allows for development of test programs in the C programming language. Additional techniques that may be utilized include behavioral representations of a portion of the design (for performance and capacity) as well as transactors, protocol watchers and similar techniques.

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For more information on the benefits of involving Advanced Architectures in this process, call our offices today.