LVS and Design Rule Checking

LVS (Layout versus schematic) checks whether the schematic and layout were indeed identical. While schematics are rarely used any more in digital design the requirement to verify that the final layout matches the intended design remains. Therefore, today's LVS has been augmented by, formal equivalence checking which checks whether two circuits perform exactly the same function without demanding isomorphism.

DRC (Design Rule Checking) determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called design rules. Design rule checking is a major step during physical verification signoff on the design, which also involves XOR checks, ERC (electrical rule check) and antenna checks. For advanced processes some fabs also insist upon the use of more restricted rules to improve yield.

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What else needs to be done?

There is a litany of tasks to complete prior to release of design to a foundry. Here is a sample:

  • Signal Integrity -- IR drop, Electro-migration, Static Timing
  • Pin-out power/ground distribution analysis
  • Simultaneous switching output analysis
  • Substrate noise analysis
  • Clock distribution - tap adjustment - clock insertion delay tuning
  • Power distribution analysis
  • Final extraction
  • View generation
  • Manufacturing test vectors for wafer sort
  • Manufacturing test vectors to packaged part test
  • Wire and bond diagrams
  • Package marking instructions
  • Final design review

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As a well-respected architecture firm, Advanced Architectures is an excellent choice for those in need of physical ASIC design.

Our thorough and detailed studies have helped many clients make informed decisions about the physical design of an ASIC and the very large suite of tasks that must be performed before a design is ready to be submitted to a foundry fabrication.

To learn more about how we can assist you, give us a call today.