SoC System Manager (SSM) is a hardware-software “subsystem” IP which decouples SoC system management functions, such as power, security, error recovery, and boot sequencing, from the specific design, and consolidates these tasks, promoting high reuse and faster hardware-software integration. Add SSM virtualization to your SoC architecture and save time and money.
IoT configurable Microcontroller is an A2P3 with a configurable collection of other A2 IP in a ready-built framework ready to be deployed in an SoC.
Application Adaptive Processor is flexible processor architecture based on innovative “fine-grain” micro-architecture configurability and an expandable instruction set. The flexibility of A2P enables a basic architecture to be developed for low power applications. Available with secure debug interface, breakpoint modules and jumptrace mechanism. A complete toolset and IDE is available from Adveda.
Our latest processor iteration due to be released in Q4 2018. It features higher performance, lower power than A2P3 and also allow SIMD co-processors especially tuned for AI processing to be included.
A high performance SoC interconnect system designed for use in synthesizable designs. It is specifically developed to meet the challenges of multiprocessor and multiple DMA / IO processor designs. A2B is designed to have the highest possible occupancy so that the sustainable bus bandwidth closely approaches the available peak bandwidth of a given configuration.
A Register interconnect mechanism between control registers in an ASIC design and any number of control devices; CPUs, debug ports etc.. The bus is especially suited for synthesizable designs. It is specifically developed to meet the challenges of long interconnect delays in large System-on-chip designs and can be tailored to match system clock rates.
The Queue Manager creates and maintains queues in memory for use in interprocess communication and I/O device communication with processors in a system. It is capable of multiple queue coalescence and prioritization. These features provide significant performance improvement especially in multiprocessor applications or even single processor systems with multiple I/O mechanisms. In many applications the use of an RTOS can be avoided altogether freeing-up CPU cycles to do application work.
A dual SHA-256 pipeline suitable for Bitcoin mining. It is designed for extreme power efficiency for deep sub-micron geometries. We can also provide hard macros of multiple pipelines down to 7nm
IN DEVELOPMENT: an advanced architecture for the realization of Altcoin mining at better than GPU efficiency. Based on our long history of SIMD and multi-processor systems.
A2FS Single Precision IEEE-754 complete FPU with available direct connect to A2P3 & A2P4.
A2FD Double & Single Precision IEEE-754 complete FPU with available direct connect to A2P3 & A2P4.
A2FH Half Precision IEEE-754R complete FPU for graphics processing.